HPC Next: Reflections and Progress on the RISC-V Ecosystem

RISC-V is an open standard instruction set architecture (ISA) enabling the open development of CPUs and a shared software ecosystem. There are already over 30 billion RISC-V cores, which are accelerating rapidly and it was recently predicted that RISC-V will have over 33% market penetration by 2030. Nonetheless, for all the successes that RISC-V has enjoyed, it is yet to become popular in HPC. Recent advances, however, such as data center RISC-V-based CPUs and PCIe accelerators, mean that this technology is becoming a more realistic proposition for our workloads.

This BoF aims to connect the RISC-V and HPC communities. In recent years there have been significant investments made in RISC-V, especially across Europe, and great advances in the ecosystem, but a key unanswered question is strong reasoning around what RISC-V can offer to HPC. Therefore, driven by this challenge set to us by RISC-V International, who are the standards body, in this session we look to identify key reasons and priorities around why HPC could be adopting RISC-V. We will identify key challenges felt by our community and explore how efforts in RISC-V could have the potential to address these.

The overarching outcome from this session will be a set of new capabilities that RISC-V can deliver to HPC, and this will be written up in a white paper and published with RISC-V International to help form part of their HPC strategy.

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Organizers:

• Nick Brown
• Teresa Cervero