Leveraging SmartNICs for HPC Applications
Monday, June 22, 2026 9:00 AM to 1:00 PM · 4 hr. (Europe/Berlin)
Hall X11 - 1st Floor
Tutorial
Composable Disaggregated InfrastructureEducation and TrainingHPC in the Cloud and HPC ContainersNetworking and Interconnects
Information
The past few years have witnessed an increased level of support for and deployment of programmable network adapters, known as ``SmartNICs". These enhanced network devices offer standard packet processing capabilities as well as advanced ``in-network'' computing features built around programmable lightweight processing cores, FPGAs, and even CPU- and GPU-based platforms capable of running separate operating systems. SmartNICs have gained rapid adoption for data center tasks, including infrastructure management, packet filtering, and I/O acceleration. Increasingly these devices are also being explored for high-performance computing (HPC) and AI application acceleration.
This tutorial offers an in-depth exploration of the state-of-the-art for SmartNICs and the emerging software ecosystems supporting them. Attendees will engage in hands-on exercises to better understand how to take advantage of SmartNICs for accelerating HPC and AI applications. Specific topics include MPI and OpenMP offloading, algorithmic modifications to utilize SmartNIC processors, in-line packet processing frameworks like P4, security and containerization efforts, and I/O acceleration techniques. Participants will have the opportunity to execute these exercises using cutting-edge SmartNICs like NVIDIA's BlueField-3 Data Processing Unit (DPU) and a cloud-based Netlab environment. The tutorial presenters will discuss additional techniques for optimizing applications to harness SmartNICs as communication accelerators in HPC systems.
Contributors:
This tutorial offers an in-depth exploration of the state-of-the-art for SmartNICs and the emerging software ecosystems supporting them. Attendees will engage in hands-on exercises to better understand how to take advantage of SmartNICs for accelerating HPC and AI applications. Specific topics include MPI and OpenMP offloading, algorithmic modifications to utilize SmartNIC processors, in-line packet processing frameworks like P4, security and containerization efforts, and I/O acceleration techniques. Participants will have the opportunity to execute these exercises using cutting-edge SmartNICs like NVIDIA's BlueField-3 Data Processing Unit (DPU) and a cloud-based Netlab environment. The tutorial presenters will discuss additional techniques for optimizing applications to harness SmartNICs as communication accelerators in HPC systems.
Contributors:
Format
on-site
Targeted Audience
This tutorial is intended for HPC users, application developers, researchers and developers of programming models and communication libraries, as well as tool developers who are interested in leveraging next-generation SmartNICs for HPC applications. Hands-on interaction with an HPC cluster will be offered to all interested attendees.
Beginner Level
60%
Intermediate Level
40%
Prerequesites
Attendees need to have a laptop and public GitHub account to participate in the hands on portion of the tutorial. Basic ability to read C code, understanding of how to run MPI applications, and familiarity with Linux command-line execution should be all that is required for attendees to complete the suggested exercises.
