

Advanced Memory Architecture
Thursday, June 25, 2026 9:00 AM to 10:00 AM · 1 hr. (Europe/Berlin)
Hall 4 - Ground Floor
Panel
Composable Disaggregated InfrastructureMemory Technologies and Hierarchies
Information
One of the main challenges limiting the attainable performance for real-world applications on HPC systems is the von-Neumann bottleneck: Data located on storage (and then memory) needs to reach the computational units as quickly as possible, but bandwidth and latency are never good enough on powerful CPUs and GPUs. For applications dealing with very large amounts of data (e.g., AI training) this bottleneck is even more painful. This panel will bring together researchers and vendors of memory devices working on various innovative approaches to tackle the memory wall such as memristors, in-memory computing, or memory disaggregation.
Format
on-demandon-site
Intermediate Level
100%
Speakers

Estela Suarez
Division Leader Novel System Architecture DesignForschungszentrum Juelich GmbH, University of Bonn
John Shalf
Senior ScientistLawrence Berkeley National Laboratory, LBNL
Abu Sebastian
Distinguished Research ScientistIBM ResearchDF
Dietmar Fey
Friedrich-Alexander-University Erlangen-Nuremberg (FAU)ND
Nicolas Dubé
Corporate Vice-President, Datacenter Systems and SolutionsIntel Corporation